1. Technical Field
The present invention relates to a DLL circuit of a semiconductor memory apparatus and a method of delaying and locking a clock in a semiconductor memory apparatus, in particular, a DLL circuit of a semiconductor memory apparatus and a method of delaying and locking a clock in a semiconductor memory apparatus, which can be utilized regardless of the frequency of a clock.
2. Related Art
Generally, a DLL circuit is used to supply an internal clock having a phase earlier than that of a reference clock by converting an external clock by a predetermined time. The internal clock is generated so it operates in synchronization with the external clock in a semiconductor memory apparatus having high integration, such as synchronous DRAM (SDRAM).
In particular, when the external clock is input to a clock input buffer through an input pin, the internal clock is generated from the clock input buffer. The internal clock controls a data output buffer such that data is output to the outside. At this time, the internal clock is delayed from the external clock by a predetermined time due to a clock buffer. The output data also delayed from the internal clock by a predetermined time is output from a data output buffer.
Therefore, there is a problem in that the output data is output after being delayed for a considerable time longer than the external clock. In other words, a time at which the data is output after the external clock is applied, that is, an output data access time, becomes long.
In order to solve the above-mentioned problem, a DLL circuit should cause an internal clock to have a phase earlier than the external clock by a predetermined time, such that output data can be output without being delayed with respect to the external clock. That is, the DLL circuit receives an external clock and generates an internal clock having a phase earlier than the external clock by a predetermined time. The internal clock is used as a reference clock in a data output buffer or the like.
Hereinafter, a DLL circuit according to the related art will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the internal structure of a DLL circuit of a semiconductor memory apparatus according to the related art.
The DLL circuit shown in FIG. 1 includes: a clock buffer 10 that converts the amplitude of an external clock clk_ext and generates a first internal clock clk_int_1; a delay unit 20 that sets a delay time to the first internal clock clk_int_1, performs a push/pull delay with respect to the delayed first internal clock clk_int_1 in response to the inputs of first and second phase control signals phc_1 and phc_2, and then generates a second internal clock clk_int_2; a duty cycle compensation unit 30 that detects the duty cycle of the second internal clock clk_int_2 and generates a third internal clock clk_int_3 in which the duty ratio is fifty percent; a phase splitter 40 that controls the phase of the third internal clock clk_int_3 and generates and outputs a rising clock rclk and a falling clock fclk; a clock divider 50 that divides the frequency of the third internal clock clk_int_3 by a predetermined value and generates a divided clock clk_div; a delay compensation unit 60 that delays the divided clock clk_div and generates a feedback clock clk_fb so as to compensate for a delayed time set by delay elements existing on a path in which the second internal clock clk_int_2 is output to the outside of a semiconductor memory apparatus; and a phase sensing unit 70 that senses a phase difference between the first internal clock clk_int_1 and the corresponding feedback clock clk_fb, generates the first and second phase control signals phc_1 and phc_2, and transmits the generated first and second phase control signals phc_1 and phc_2 to the delay unit 20.
When the external clock clk_ext is transmitted to the clock buffer 10 from the outside of the semiconductor memory apparatus, the clock buffer 10 converts the external clock clk_ext having a small amplitude into the first internal clock clk_int_1 having a large amplitude, and transmits the first internal clock clk_int_1 to the delay unit 20. The delay unit 20 delays the first internal clock clk_int_1 by a predetermined time and outputs the first internal clock clk_int_1 as the second internal clock clk_int_2. At this time, in the second internal clock clk_int_2, a time ratio is not exactly equal between a high level cycle and a low level cycle. Therefore, the duty cycle compensation unit 30 detects the duty cycle of the second internal clock clk_int_2 and then outputs the third internal clock clk_int_3 having adjusted the duty ratio thereof.
The clock divider 50 is used for a high frequency external clock clk_ext. This is because when the external clock clk_ext has a high frequency, due to the first to third internal clocks clk_int_1 to clk_int_3 and the feedback clock clk_fb changing to high frequency clocks, the high frequency clocks may be become inactive. Further, it becomes difficult for the phase sensing unit 70 to compare the first internal clock clk_int_1 and the feedback clock clk_fb. Therefore, the clock divider 50 is used in a case when the external clock signal clk_ext has a high frequency so as to divide the frequency of the third internal clock clk_int_3 and generate the divided clock clk_div. If the clock divider 50 is set to divide the frequency of the third internal clock clk_int_3 in half, the cycle of the divided clock clk_div becomes two times larger than the cycle of the third internal clock clk_int_3.
The delay compensating unit 60 has delay values of delay elements existing on a path in which the second internal clock clk_int_2 is output from the delay unit 20 to the outside of the semiconductor memory apparatus. Accordingly, the delay compensating unit 60 sets a predetermined delay time to the divided clock clk_div to compensate the delay values of the delay elements, and generates the feedback clock clk_fb. The phase sensing unit 70 compares the phases of the first internal clock clk_int_1 and the feedback clock clk_fb and generates the first and second phase control signals phc_1 and phc_2. At this time, the first phase control signal phc_1 has a logical value inverse to that of the second phase control signal phc_2. When the first control signal phc_1 is enabled, the delay unit 20 sets a positive delay time to the first internal clock clk_int_1 and performs a push delay operation. When the second control signal phc_2 is enabled, the delay unit 20 sets a negative delay time to the first internal clock clk_int_1 and performs a pull delay operation.
FIG. 2 is a circuit diagram showing the internal structure of the phase sensing unit shown in FIG. 1.
The phase sensing unit 70 includes: a first flip-flop FF1 that receives the feedback clock clk_fb input at a rising edge time of the first internal clock clk_int_1 and outputs the first phase control signal phc_; and a first inverter IV1 that inverts the first phase control signal phc_1 and outputs the second phase control signal phc_2.
When the feedback clock clk_fb has a phase earlier than that of the first internal clock clk_int_1, the phase of the feedback clock clk_fb is a high level at a rising edge time of the first internal clock clk_int_1. Accordingly, the first phase control signal phc_1 is enabled, that is, the first phase control signal phc_1 changes to a high level, and the second phase control signal phc_2 is disabled, that is, the second phase control signal phc_2 changes to a low level. In contrast, when the first internal clock clk_int_1 has a phase earlier than that of the feedback clock clk_fb, the phase of the feedback clock clk_fb is a low level at a rising edge time of the first internal clock clk_int_1. Accordingly, the first phase control signal phc_1 is disabled, that is, the first phase control signal phc_1 changes to a low level and the second phase control signal phc_2 is enabled, that is, the second phase control signal phc_2 changes to a high level. That is, the phase sensing unit 70 compares the phases of the feedback clock clk_fb on the basis of the first internal clock clk_int_1 as a reference clock so as to control the operation of the delay unit 20.
FIGS. 3A and 3B are graphs for explaining the operation of the DLL circuit of a semiconductor memory apparatus according to the related art.
As shown in FIG. 3A, the feedback clock clk_fb is a clock signal having a cycle two times larger than that of the first internal clock clk_int_1. In this case, since the feedback clock clk_fb has a phase earlier than that of the first internal clock clk_int_1, the first phase control signal phc_1 should be enabled. However, when the phase of the feedback clock clk_fb is determined at a rising edge time of the first internal clock clk_int_1 and the first and second phase control signals phc_1 and phc_2 are generated, the first phase control signal phc_1 becomes a pulse signal having a phase at a high level and second phase control signal phc_2 becomes a pulse signal having a phase at a low level. Therefore, the delay unit 20 which receives the first and second phase control signals phc_1 and phc_2 and delays the first internal clock clk_int_1 repeatedly performs the push delay operation and the pull delay operation. As a result, it causes a problem in that the phase of the first internal clock clk_int_1 is not consistent with the phase of the feedback clock clk_fb.
FIG. 3B shows the operation of the DLL circuit in which the described problems are solved. FIG. 3B shows the operation of the DLL circuit in which the first internal clock clk_int_1 is input to the phase sensing unit 70, instead of the feedback clock clk_fb, and the feedback clock clk_fb is input to the phase sensing unit 70, instead of the first internal clock clk_int_1. That is, the phase of the first internal clock clk_int_1 is compared on the basis of the feedback clock clk_fb so as to generate the first and second phase control signals phc_1 and phc_2. In this case, the first and second phase control signals phc_1 and phc_2 are generated at a predetermined level. However, the first and second phase control signals phc_1 and phc_2 have inverse phases with respect to the case based on the first internal clock clk_int_1. Therefore, the first and second phase control signals phc_1 and phc_2 should be switched with each other and then input to the delay unit.
As described above, if the phase of the first internal clock clk_int_1 is compared on the basis of the feedback clock clk_fb, a problem in that the feedback clock clk_fb is divided can be solved. However, the phases of the first and second phase control signals phc_1 and phc_2 should be changed every two cycles of the first internal clock clk_int_1. As such, no problems occur in the case when the external clock clk_ext is a high frequency signal. However, when the external clock clk_ext is a low frequency signal, since the feedback clock clk_fb and the first internal clock clk_int_1 have a large cycle, a cycle in which the first and second phase control signals phc_1 and phc_2 are changed is large. Accordingly, an internal clock generation operation with respect to the cycle change of the external clock clk_ext is late, thereby causing problems in the performance of the DLL circuit.
As described above, if a feedback clock is generated in a DLL circuit that generates internal clocks on the basis of high frequency external clocks without using a clock divider, the feedback clock may be become inactive. However, if the feedback clock is generated by using the clock divider, there is a problem in that a reference clock and the feedback clock should be switched with each other and then input to a phase sensing unit, and a cycle in which a phase control signal for setting a delay time to a delay unit is set to a new phase. In order to solve the above-described problems, a clock divider is arbitrarily selected by a switch such as a fuse on the basis of the frequency of an external clock in the related art. Therefore, there are problems in that the clock divider should be selectively used on the basis of the frequency of the external clock and the connection of the input/output terminal of the phase sensing unit should be changed. Accordingly, the cost and time necessary for developing and utilizing the DLL circuit are inefficiently managed.